1. Field of the Invention
The present invention relates to a semiconductor device including a multi-level interconnection structure provided on a semiconductor substrate, and a production method for the semiconductor device.
2. Description of Related Art
A multi-level interconnection structure provided on a semiconductor substrate includes a plurality of interconnection layers stacked one on another. A method of forming each of the interconnection layers include the steps of: forming an interconnection; burying the interconnection layer with an insulative film; and planarizing a surface of the insulative film by a chemical mechanical polishing (CMP) process.
The CMP planarization step is performed by polishing the surface of the insulative film with a polishing pad being pressed against the surface of the insulative film. A polishing pad pressing pressure is lower in a higher density region in which the interconnection is provided at a higher layout density, and higher in a lower density region in which the interconnection is provided at a lower layout density. Therefore, a so-called global step is formed between the higher density region (dense region) and the lower density region (sparse region). The global step generally reduces the accuracy of a photolithography process to be performed for forming an upper-level interconnection on the surface of the insulative film. In an exposure step, particularly, it is difficult to provide a properly focused state over the entire surface of the insulative film and hence to form a minute interconnection pattern at a higher level of accuracy.
In the prior art disclosed in US2002/157076A1, the entire semiconductor wafer is divided into rectangular regions, and the pattern density is calculated for each of the divided regions. More specifically, the area ratio of an electrically conductive pattern (metal interconnection pattern) to each of the regions is calculated as the pattern density. If the pattern density is not greater than a threshold, the region is defined as the sparse region. In the sparse region, a dummy pattern is provided in addition to the electrically conductive pattern (metal interconnection pattern). With the additional provision of the dummy pattern, the electrically conductive pattern and the dummy pattern are arranged at a uniform layout density as a whole in the sparse region. This reduces the variation in polishing pad pressing pressure, thereby reducing the global step.
In the prior art, the global steps on the respective interconnection layers are reduced. However, it is impossible to completely planarize the surfaces of the respective interconnection layers. With the plurality of interconnection layers stacked one on another, therefore, a larger global step is likely to occur on a surface of an upper interconnection layer.
More specifically, even if the dummy pattern is provided in a sparse region of a first interconnection layer, there is a possibility that the overall layout density of the electrically conductive pattern and the dummy pattern in the sparse region is still lower than the layout density of the electrically conductive pattern in a dense region of the first interconnection layer. In this case, the planarized surface of the insulative film is located at a higher level in the dense region than in the sparse region in which the dummy pattern is provided. On the other hand, it is assumed that a sparse region of a second interconnection layer on the first interconnection layer is located on the dense region of the first interconnection layer. In this case, a dummy pattern is provided in the sparse region of the second interconnection layer. As a result, there is a possibility that the overall layout density of the electrically conductive pattern and the dummy pattern in the sparse region of the second interconnection layer is higher than the layout density of the electrically conductive pattern of the second interconnection layer on the sparse region of the first interconnection layer. In this case, the insulative film of the second interconnection layer is thicker in the sparse region of the second interconnection layer (on the dense region of the first interconnection layer), and is thinner in a region of the second interconnection layer on the sparse region of the first interconnection layer. Since the thicker insulative film regions of the first interconnection layer and the second interconnection layer are superposed one on the other, the global step on the surface of the second interconnection layer is increased. In the prior art of US2002/157076A1 in which the thicknesses of the respective interconnection layers are made uniform, the global step is increased by stacking the interconnection layers one on another, thereby reducing the accuracy of the photolithography process to be performed on the upper interconnection layer.